1. Field of the Invention
The present invention relates to semiconductor wafer inspection systems and semiconductor wafer inspection methods.
2. Brief Description of Related Art
Semiconductor circuits are manufactured by forming micro-patterned structures on a flat semiconductor wafer substrate using lithographic methods. A wafer substrate may have a diameter of about 300 mm, wherein several hundred circuits are arranged in individual dies typically having diameters in the order of some millimeters to some 10 mm, wherein the structures of the semiconductor circuits may have dimensions below 0.1 μm. It is desirable to detect defects in the manufactured patterns and deficiencies of a manufacturing process at early stages of the semiconductor manufacture.
Several techniques are known for inspection of semiconductor substrates. These techniques try to locate defects on a wafer substrate in a coordinate system defined relative to the wafer substrate. The coordinate system of the wafer may be defined such that it has its origin in a center of the wafer, wherein an orientation of the coordinate system is defined relative to a wafer notch.
In a process of semiconductor wafer inspection it is necessary to map coordinates of defects as detected in a coordinate system of an inspection tool to the coordinate system of the wafer. Conventional inspection methods involve special tools and methods for detecting a wafer edge to finally determine the center of a particular wafer on the inspection, and to detect the wafer notch to determine the orientation of the wafer.
The tools and methods for wafer edge and notch detection have sometimes been found to be insufficient and complicated.